1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically, it relates to a semiconductor device having a hierarchical power supply line structure.
2. Description of the Prior Art
The withstand voltage of a transistor is reduced as the transistor is refined, and hence the operating voltage must inevitably be lowered. For battery driving which is prerequisite for a portable device, an operation under a low voltage and low power is essential.
When the operating voltage is lowered, however, the operating speed is reduced in general. In order to implement a low-voltage operation without reducing the operating speed, therefore, the threshold voltage of a MOS transistor must be lowered. If the threshold voltage is excessively lowered, however, the transistor cannot be sufficiently cut off but an unnegligible subthreshold current flows also when the transistor is in an OFF state. Thus, low power consumption, which is the maximum feature of a conventional CMOS circuit, is lost.
FIG. 44 is a circuit diagram showing the structure of an invertor 1500 in a conventional semiconductor device.
Referring to FIG. 44, the invertor 1500 includes a P-channel MOS transistor 1501 having a gate receiving an input signal IN and a source coupled to a power supply potential Vdd, and an N-channel MOS transistor 1502 having a gate receiving the input signal IN, a source coupled to a ground potential Vss and a drain connected to that of the P-channel MOS transistor 1501.
The drain of the N-channel MOS transistor 1502 outputs an output signal OUT. Assuming that Vt represents the threshold voltage of the N-channel MOS transistor 1502, the operating speed of the transistor 1502 is substantially in inverse proportion to Vddxe2x88x92Vt. In order to suppress reduction of the operating speed, therefore, the threshold voltage Vt must be reduced in response to reduction of the power supply potential Vdd.
If the threshold value Vt is excessively lowered, however, an unnegligible subthreshold current IL flows in the N-channel MOS transistor 1502 also when a potential 0 V is supplied as the input signal IN.
FIG. 45 illustrates the relation between a gate-to-source voltage VGS and a drain current IDS of the N-channel MOS transistor 1502.
This figure shows change of the drain current IDS following change of the gate-to-source voltage VGS around the threshold voltage Vt. The drain current IDS is logarithmically plotted on the vertical line.
Referring to FIG. 45, it is assumed that the gate-to-source voltage VGS reaches the threshold voltage Vt when a constant current 10 flows in the transistor 1502 in a line 1504. Consider the case of employing an N-channel MOS transistor having a lower threshold voltage Vt2 in place of the threshold voltage Vt, to be usable under a low power supply voltage.
A line 1506 shows the relation between the drain current IDS and the gate-to-source voltage VGS of this N-channel MOS transistor. Comparing the values of the drain currents IDS on the lines 1504 and 1506 when the gate-to-source voltages VGS are zero, the value of the drain current IDS rises from IL to IL2. Therefore, the subthreshold current cannot be neglected following high integration and reduction of the power supply voltage, and increase of a standby current causes a critical problem in a portable device driven by a battery.
FIG. 46 is a circuit diagram showing an invertor 1510 reducing a subthreshold current by switching a source voltage proposed in general.
Referring to FIG. 46, the invertor 1510 includes an invertor 1511 having a power supply node coupled with a power supply potential Vdd and a ground node connected to a node N100 for receiving an input signal IN and outputting an output signal OUT, and an N-channel MOS transistor 1516 having a gate receiving a control signal SCRC, a drain connected to the node N100 and a source coupled to a ground potential Vss.
The invertor 1511 includes a P-channel MOS transistor 1512 having a gate receiving the input signal IN, a source connected to the power supply node and a drain connected to an output node, and an N-channel MOS transistor 1514 having a gate receiving the input signal IN, a source connected to the node N100 and a drain connected to the output node.
FIGS. 47A and 47B are diagrams for illustrating types of transistors. FIG. 47A is a diagram for illustrating the symbol of a transistor 1518 having a high threshold voltage, and FIG. 47B is a diagram for illustrating the symbol of a transistor 1520 having a low threshold voltage.
Referring to FIGS. 47A and 47B, it is assumed that the symbol of the transistor 1518 shown in FIG. 47A stands for a transistor having a high threshold voltage, and the symbol of the transistor 1520 shown in FIG. 47B stands for a transistor having a low threshold voltage.
Referring again to FIG. 46, this circuit renders the N-channel MOS transistor 1516 conductive, sets the potential VN of the node N100 at the ground potential Vss and lets the invertor 1511 perform an ordinary logic operation with the control signal SCRC in ordinary operation.
When the potential supplied by the input signal IN is at a low level, the P-channel MOS transistor 1512 is rendered conductive while the N-channel MOS transistor 1514 is rendered non-conductive, and the output potential of the output signal OUT goes high. In this case, a subthreshold current flows in the non-conductive N-channel MOS transistor 1514 and a current resulting from the subthreshold current flows from the power supply node supplied with the power supply potential Vdd to the ground node supplied with the ground potential Vss.
When the input level of the input signal IN is high, on the other hand, the P-channel MOS transistor 1512 is rendered non-conductive while the N-channel MOS transistor 1514 is rendered conductive, and the level of the output signal OUT goes low. In this case, a subthreshold current flows in the non-conductive P-channel MOS transistor 1512, to flow from the power supply node to the ground node. Thus, power is unavoidably consumed by the subthreshold current in an ordinary operating state.
When employing this circuit during a period when it is recognized that input logic is previously fixed, e.g., during a standby period when the chip is in a standby state, power consumption by the subthreshold current can be reduced.
Assuming that the input signal IN for this circuit goes low in the standby state, the P-channel MOS transistor 1512 is rendered conductive while the N-channel MOS transistor 1514 is rendered non-conductive. At this time, the output signal OUT is at a high level.
When switching the control signal SCRC from a high level to a low level for switching control from an operating state to the standby state, the N-channel MOS transistor 1516 is rendered non-conductive. The absolute value of the threshold voltage of the N-channel MOS transistor 1516 is greater than that of the N-channel MOS transistor 1514, and hence a subthreshold current flowing through the N-channel MOS transistor 1516 is remarkably smaller than that flowing in the N-channel MOS transistor 1514.
Thus, a leakage current flowing from the power supply node to the ground node depends on the subthreshold current of the N-channel MOS transistor 1516, and hence power consumption by the subthreshold current can be reduced in the standby state.
Despite the high threshold voltage of the N-channel MOS transistor 1516, the operating speed of the invertor 1511 is not influenced when the N-channel MOS transistor 1516 is in a conductive state. Further, the speed for switching from the operating state to the standby state may not be so high as the operating speed of the invertor 1511, and hence no problem arises even if the N-channel MOS transistor 1516 has a high threshold voltage and a slightly low operating speed.
When the input signal IN is at a low level, as hereinabove described, the circuit can be set in the standby state through the control signal SCRC while statistically holding the output potential of the output signal OUT.
FIG. 48 is a waveform diagram for illustrating change of the sub ground potential VN of the node N100 around switching of the control signal SCRC.
Referring to FIGS. 46 and 48, the N-channel MOS transistor 1516 is rendered non-conductive when the level of the control signal SCRC changes from the power supply potential Vss to 0 V. Then, the subthreshold current flows in the N-channel MOS transistor 1516, and a current of the same magnitude also flows in the N-channel MOS transistor 1514.
Slightly after switching the control signal SCRC, therefore, the potential of the node N100 reaches 0 V+Vvn slightly above 0 V.
FIG. 49 is a graph for illustrating the relation between a drain current IDS flowing in the N-channel MOS transistor 1514 in the standby state and a gate-to-source voltage VGS.
Referring to FIGS. 46 and 49, the potential VN of the node N100 reaches Vvn in the standby state, and the level of the input signal IN is 0 V at this time. In the N-channel MOS transistor 1514, therefore, the gate-to-source voltage VGS reaches a negative level xe2x88x92Vvn. It is understood from the graph shown in FIG. 49 that the subthreshold current flowing in the N-channel MOS transistor 1514 is reduced from IL to IL1 due to the provision of the N-channel MOS transistor 1516. This current IL1 is also the subthreshold current of the N-channel MOS transistor 1516.
If the input signal IN goes high in the standby state, a similar effect can be attained by inserting a P-channel MOS transistor having a high threshold voltage on the power supply node side of the invertor 1511.
FIG. 50 is a circuit diagram for illustrating the structure of a circuit 1530 employing serially connected invertors of FIG. 46 and the state of each node in a standby state.
Referring to FIG. 50, the circuit 1530 includes an invertor 1536 receiving an input signal IN, inverting the same and outputting the inverted signal to a node N106, an invertor 1538 receiving the potential of the node N106, inverting the same and outputting the inverted potential to a node N108, an invertor 1540 receiving the potential of the node N108, inverting the same and outputting the inverted potential to a node N110, and an invertor 1542 receiving the potential of the node N10, inverting the same and outputting an output signal OUT.
The circuit 1530 further includes a P-channel MOS transistor 1532 having a gate receiving a control signal /SCRC, a source coupled to a power supply potential Vdd and a drain connected to a node N102 (sub power supply line), and an N-channel MOS transistor 1534 having a gate receiving a control signal SCRC, a source coupled to a ground potential Vss and a drain connected to a node N104 (sub ground line).
Power supply nodes of the invertors 1536 and 1540 are coupled to the power supply potential Vdd. Power supply nodes of the invertors 1538 and 1542 are connected to the node N102. Ground nodes of the invertors 1536 and 1540 are connected to the node N104. Ground nodes of the invertors 1538 and 1542 are coupled to the ground potential Vss.
The P-channel MOS transistor 1532 has a threshold voltage whose absolute value is greater than the threshold voltages of P-channel MOS transistors included in the invertors 1536 to 1542. The N-channel MOS transistor 1534 has a threshold voltage whose absolute value is greater than the threshold voltages of N-channel MOS transistors included in the invertors 1536 to 1542.
The invertors 1536 to 1542 are similar in structure to the invertor 1511 shown in FIG. 46, and hence redundant description is omitted.
A standby state of the circuit 1530 is now described.
In the standby state, the control signal /SCRC is set high and the node N102 is cut off from the power supply nodes. The control signal SCRC is set low and the node N104 is cut off from the ground nodes. In the standby state, the input signal IN is at a low level, the nodes N106 and N110 go high, and the node N108 and the output signal OUT go low. The potential VN of the node N104 is slightly higher than the ground potential Vss, and subthreshold currents of the N-channel MOS transistors included in the invertors 1536 and 1540 are reduced. The potential VP of the node N102 is slightly lower than the power supply potential Vdd, and subthreshold currents of the P-channel MOS transistors included in the invertors 1538 and 1542 are reduced.
FIG. 51 is a circuit diagram for illustrating the state of each node in an ordinary operating state of the circuit 1530.
In the ordinary operating state, a low level is supplied as the control signal /SCRC, and the potential VP of the node N102 reaches the power supply potential Vdd. Further, a high level is supplied as the control signal SCRC, and the potential VN of the node N104 reaches the ground potential Vss. In this state, the input signal IN is properly switched to a high or low level, to perform a logic operation.
FIG. 51 shows the state of each node when a high level is supplied as the input signal IN. When the input signal IN is high, the nodes N106 and N110 go low while the node N108 and the output signal OUT go high.
When a low level is supplied as the input signal IN, the nodes N106, N110 and N108 and the output signal OUT are in states similar to those shown in FIG. 50, and hence redundant description is omitted.
When employing a hierarchical power supply line structure for reducing subthreshold currents as described above, a P-channel MOS transistor QHP and an N-channel MOS transistor QHN for controlling a sub power supply potential VP and a sub ground potential VN must be controlled. These transistors QHP and QNP must be adjusted in size in response to current consumption of a circuit connected to a sub power supply line.
If the transistor size is smaller than that corresponding to the consumed current in this case, a potential drop is caused on the sub power supply line due to current consumption of the circuit, to increase noise of the sub power supply line and exert a bad influence on the circuit operating speed.
When employing the hierarchical power supply structure, the size of the transistor for driving the sub power supply line must be adjusted to an optimum state, while this adjustment is hard to attain.
FIG. 52 is a waveform diagram for illustrating the potential VP of the sub power supply line and the potential VN of the sub ground line when the circuit 1530 described with reference to FIGS. 50 and 51 repeats a standby state and an operating state.
Referring to FIGS. 51 and 52, the power supply potential Vdd rises before a time t1. At the time t1, the control signals SCRC and ISCRC are set to inactivate the sub power supply line and the sub ground line. In other words, the circuit 1530 is set in the standby state.
The potential difference xcex94Vd0 between the power supply potential Vdd and the potential VP of the sub power supply line depends on the threshold voltage Vtph and the gate width of the P-channel MOS transistor 1532. The potential difference xcex94Vg0 between the ground potential Vss and the potential VN of the sub ground line depends on the threshold voltage Vtnh and the gate width of the N-channel MOS transistor 1534. Considering the worst state, xcex94Vd0=Vtph and xcex94Vg0=Vtnh when taking the maximum values.
At a time t2, the control signals SCRC and /SCRC change to activate the sub power supply line and the sub ground line, and the circuit enters an active state. At this time, fluctuation of the potential levels is approximately 1 V in total.
When the potentials VP and VN of the sub power supply line and the sub ground line remarkably fluctuate, considerable time is required for activating the circuit. Therefore, it is important when to switch the control signals SCRC and /SCRC for the timing of the circuit operation. The operating speed of the circuit is reduced if the switching timing for the control signals SCRC and /SCRC is late, while the subthreshold currents are increased to increase power consumption if the switching timing is too early. Thus, it is hard to decide the timing.
Further, the remarkable potential difference around starting itself causes increase of the starting time for activating the sub power supply line and the sub ground line. If the potential difference is excessively small, however, the subthreshold currents cannot be suppressed. It is difficult to set the potential difference at an optimum value due to fluctuation of the threshold voltages etc. resulting from dispersion of process parameters in fabrication.
An object of the present invention is to provide a semiconductor device having a hierarchical power supply structure, which can reduce noise caused on a sub power supply line and a sub ground line for increasing the speed of a circuit operation.
Another object of the present invention is to provide a semiconductor device, which can adjust a timing for activating a sub power supply line and a sub ground line with respect to an operation timing of an internal circuit.
Still another object of the present invention is to provide a semiconductor device, which can check and adjust optimum potentials of a sub power supply line and a sub ground line in a standby state.
Briefly stated, the present invention is directed to a semiconductor device comprising a first main power supply line, a second main power supply line, a first sub power supply line, a second sub power supply line, a first internal circuit, a first connection circuit, a second connection circuit, and a power supply noise reduction circuit.
The first main power supply line is supplied with a first power supply potential. The second main power supply line is supplied with a second power supply potential lower than the first power supply potential. The first sub power supply line is provided in correspondence to the first main power supply line. The second sub power supply line is provided in correspondence to the second main power supply line. The first internal circuit has first and second power supply nodes connected to the first and second sub power supply lines respectively, receives at least one input signal and performs a prescribed operation. The first connection circuit connects the first main power supply line with the first sub power supply line in an operating mode, and separates the first main power supply line from the first sub power supply line in a standby mode. The second connection circuit connects the second main power supply line with the second sub power supply line in the operating mode, and separates the second main power supply line from the second sub power supply line in the standby mode. The power supply noise reduction circuit is connected to the first and second main power supply lines and the first and second sub power supply lines. The power supply noise reduction circuit includes a first capacitor connected between the first main power supply line and the second sub power supply line, a second capacitor connected between the first sub power supply line and the second main power supply line, and a third capacitor connected between the first sub power supply line and the second sub power supply line.
According to another aspect of the present invention, a semiconductor device comprises a first main power supply line, a second main power supply line, a first sub power supply line, a second sub power supply line, a first internal circuit, a first connection circuit and a control circuit.
The first main power supply line is supplied with a first power supply potential. The second main power supply line is supplied with a second power supply potential lower than the first power supply potential. The first sub power supply line is provided in correspondence to the first main power supply line. The second sub power supply line is provided in correspondence to the second main power supply line. The first internal circuit is connected to the first sub power supply line and the second sub power supply line, and performs a prescribed operation in response to at least one input signal. The first connection circuit connects the first main power supply line with the first sub power supply line in response to a first activation signal. The control circuit generates the first activation signal.
The control circuit includes a timing change circuit changing the activation timing for the first activation signal with reference to an input timing of an input signal in a test mode.
According to still another aspect of the present invention, a semiconductor device comprises a first main power supply line, a second main power supply line, a first sub power supply line, a second sub power supply line, a first internal circuit, a first control circuit and a second control circuit.
The first main power supply line is supplied with a first power supply potential. The second main power supply line is supplied with a second power supply potential lower than the first power supply potential. The first sub power supply line is provided in correspondence to the first main power supply line. The second sub power supply line is provided in correspondence to the second main power supply line. The first internal circuit has first and second power supply nodes connected to the first and second sub power supply lines respectively, receives at least one input signal and performs a prescribed operation. The first control circuit connects the first main power supply line with the first sub power supply line in an operating mode, and holds the potential difference between the first main power supply line and the first sub power supply line at a prescribed first value in a standby mode. The second control circuit connects the second main power supply line with the second sub power supply line in the operating mode, and holds the potential difference between the second main power supply line and the second sub power supply line at a prescribed second value in the standby mode.
Therefore, a main advantage of the present invention resides in that, in a circuit block having a hierarchical power supply structure, the operating speed of the circuit can be improved by employing a power supply-to-power supply capacitance cell.
Another advantage of the present invention resides in that an optimum timing for activation of hierarchical power supply lines compatibly implementing a high-speed operation and reduction of a leakage current and current consumption can be evaluated through a test.
Still another advantage of the present invention resides in that the potential of a sub power supply line can be adjusted so that the optimum potential of the sub power supply line causing no leakage current can be measured.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.